1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly is suitably applied to a method of suppressing a pulse waveform, which is transmitted sequentially via logic circuits including field effect transistors, from deteriorating because of negative bias temperature instability (NBTI) or positive bias temperature instability (PBTI).
2. Description of the Related Art
It is known that a P-channel metal-oxide semiconductor (PMOS) transistor deteriorates with time because of NBTI. The aged deterioration due to NBTI is a phenomenon in which, when an ON state of the PMOS transistor continues for a long time under a high-temperature condition (e.g., when source voltage and drain voltage are 0 volt and gate voltage is negative bias), threshold voltage of the PMOS transistor rises and a current driving ability falls.
Japanese Patent Application Laid-Open No. 2006-211494 discloses a method of alternately switching, every time an enable signal EN changes to a low level, a logic level of a buffer and a flip-flop to a low-level fixed state and a high-level fixed state to thereby allow the high-level fixed period and the low-level fixed period to be regarded the same, equalizing the influence of delayed deterioration due to NBTI of the buffer, and suppressing a clock skew.
However, in the method disclosed in Japanese Patent Application Laid-Open No. 2006-211494, it is necessary to alternately switch the logic level of the buffer and the flip-flop to the low-level fixed state and the high-level fixed state even in a non-transmission period of a signal. This causes an increase in a consumed current and a circuit area.